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74F322 Octal Serial/Parallel Register with Sign Extend
April 1988 Revised April 1999
74F322 Octal Serial/Parallel Register with Sign Extend
General Description
The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the register.
Features
s Multiplexed parallel I/O ports s Separate serial input and output s Sign extend function s 3-STATE outputs for bus applications
Ordering Code:
Order Number 74F322PC Package Number N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009516.prf
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74F322
Unit Loading/Fan Out
U.L. Pin Names RE S/P SE S D 0 , D1 CP MR OE Q0 I/O0-I/O 7 Description HIGH/LOW Register Enable Input (Active LOW) Serial (HIGH) or Parallel (LOW) Mode Control Input Sign Extend Input (Active LOW) Serial Data Select Input Serial Data Inputs Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) 3-STATE Output Enable Input (Active LOW) Bi-State Serial Output Multiplexed Parallel Data Inputs or 3-STATE Parallel Data Outputs 1.0/1.0 1.0/1.0 1.0/3.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 3.5/1.083 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.8 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/-20 mA 70 A/-0.65 mA -3 mA/24 mA (20 mA)
Functional Description
The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH signal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Complement Multiplier. A HIGH signal on OE disables the 3STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.
Mode Select Table
Inputs Mode Clear MR L L Parallel Load Shift Right Sign Extend Hold H H X X X L H H H L L L H H H H H L L H X L L L H RE X X L S/P X X L SE X X X S X X X OE (Note 1) L H X CP X I/O7 L Z I7 I/O6 L Z I6 I/O5 L Z I5 Outputs I/O4 L Z I4 I/O3 L Z I3 I/O2 L Z I2 I/O1 L Z I1 I/O0 L Z I0 Q0 L L I0
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Output State = LOW-to-HIGH Transition NC = No Change Note: I7-I 0 = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I/O terminal. Note: D0, D 1 = The level of the steady-state inputs to the serial multiplexer input. Note: O7-O0 = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition.

X
D0 D1 O7
O7 O7 O7
O6 O6 O6
O5 O5 O5
O4 O4 O4
O3 O3 O3
O2 O2 O2
O1 O1 O1
O1 O1 O1
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note 1: When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected.
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74F322
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F322
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT ICEX VID IOD IIL Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current -0.6 -1.2 -1.8 IIH + IOZH IIL + IOZL IOS IZZ ICC Output Short-Circuit Current Bus Drainage Test Power Supply Current 60 -60 -150 500 90 mA A mA Max 0.0V Max VOUT = 0V VOUT = 5.25V Output Leakage Current -650 A Max VI/O = 0.5V (I/On) Output Leakage Current 70 mA mA mA A Max Max Max Max 3.75 A 0.0 4.75 10% VCC 10% VCC 2.5 2.4 2.7 2.7 0.5 0.5 5.0 7.0 0.5 50 A A mA A V Max Max Max Max 0.0 V Min V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA (Q0, I/On) IOH = -3 mA (I/On) IOH = -1 mA (Q0, I/On) IOH = -3 mA (I/On) IOL = 20 mA (Q0) IOL = 24 mA (I/On) VIN = 2.7V VIN = 7.0V (Non-I/O Inputs) VIN = 5.5V (I/On) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (RE, S/P, Dn, CP, MR, OE) VIN= 0.5V (S) VIN= 0.5V (SE) VI/O = 2.7V (I/On)
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74F322
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to Q0 Propagation Delay MR to I/On Propagation Delay MR to Q0 Output Enable Time OE to I/On Output Disable Time OE to I/On Output Enable Time S/P to I/On Output Disable Time S/P to I/On 3.0 4.0 2.0 2.0 4.5 5.5 5.0 6.0 6.5 8.5 4.5 5.0 8.0 10.0 9.0 12.0 9.0 11.0 6.0 7.0 10.5 14.0 11.5 15.5 3.0 4.0 2.0 2.0 4.5 5.5 5.0 6.0 12.5 14.5 8.0 10.0 13.5 17.0 16.5 19.5 3.0 4.0 2.0 2.0 4.5 5.5 5.0 6.0 10.0 12.0 7.0 8.0 11.5 15.0 12.5 16.5 ns ns 5.5 7.5 12.0 5.5 14.0 5.5 13.0 ns 70 3.5 5.0 3.5 3.5 6.0 VCC = +5.0V CL = 50 pF Typ 90 7.0 8.5 7.0 7.0 10.0 7.5 11.0 9.0 8.0 13.0 Max Min 50 3.5 3.5 3.5 3.5 6.0 9.5 10.0 11.0 10.0 15.0 Max Min 70 3.5 5.0 3.5 3.5 6.0 8.5 12.0 10.0 9.0 14.0 ns Max MHz ns TA = -55C to +125C CL = 50 pF TA = 0C to +75C CL = 50 pF Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tSH) tS(L) tH(H) tH(L) tS(H) tS(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC MR Pulse Width, LOW Recovery Time MR to CP 5.5 8.0 7.5 12.0 6.5 8.0 ns Setup Time, HIGH or LOW RE to CP Hold Time, HIGH or LOW RE to CP Setup Time, HIGH or LOW D0, D1 or I/On to CP Hold Time, HIGH or LOW D0, D1 or I/On to CP Setup Time, HIGH or LOW SE to CP Hold Time, HIGH or LOW SE to CP Setup Time, HIGH or LOW S/P to CP Setup Time, HIGH or LOW S to CP Hold Time, HIGH or LOW S or S/P to CP CP Pulse Width, HIGH or LOW 6.0 14.0 0 0 6.5 6.5 2.0 2.0 7.0 2.5 2.0 0.0 11.0 13.5 6.5 9.0 0 0 7.0 Max Min 14.0 18.0 0 0 8.5 8.5 3.0 3.0 9.0 11.0 2.0 1.0 13.0 21.0 8.5 11.0 1.0 0 8.0 Max Min 7.0 16.0 0 0 7.5 7.5 3.0 3.0 8.0 3.5 2.0 0.0 12.0 15.5 7.5 10.0 0 0 7.0 Max ns TA = -55C to +125C TA = 0C to +75C Units
ns ns ns ns
ns
ns ns ns ns
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74F322 Octal Serial/Parallel Register with Sign Extend
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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